Expand description
Clock Configuration
This module holds configuration types used for the system clocks. For
configuration of individual peripherals, see super::periph_helpers.
Structs§
- Clocks
Config - Div8
- This type represents a divider in the range 1..=256.
- Firc
Config - Fro16K
Config - FRO16K Configuration items
- Main
Clock Config - Osc32K
Config - OSC32K Configuration Items
- Sirc
Config - Sosc
Config - SOSC/clk_in configuration
- Spll
Config - PLL1/SPLL configuration
- VddMode
Config - VddPower
Config - Power control options for the VDD domain, including the CPU and flash memory
Enums§
- Core
Sleep - Maximum sleep depth for the CPU core
- Firc
Freq Sel - Selected FIRC frequency
- Flash
Sleep - Settings for gating power to on-chip flash
- Main
Clock Source - Main clock source
- Osc32K
CapSel - Osc32K
Coarse Gain - Coarse Gain Amplification
- Osc32K
Mode - OSC32K Operational Mode
- Sosc
Mode - The mode of the external reference clock
- Spll
Mode - Mode of operation for the SPLL/PLL1
- Spll
Source - Input clock source for the PLL1/SPLL
- VddDrive
Strength - VddLevel
- Selected VDD Power Mode