Expand description
Type-level interrupt infrastructure.
This module contains one type per interrupt. This is used for checking at compile time that the interrupts are correctly bound to HAL drivers.
As an end user, you shouldn’t need to use this module directly. Use the crate::bind_interrupts!
macro
to bind interrupts, and the [crate::interrupt
] module to manually register interrupt handlers and manipulate
interrupts directly (pending/unpending, enabling/disabling, setting the priority, etc…)
Enums§
- CACHE typelevel interrupt.
- CLOCK_POWER typelevel interrupt.
- COMP_LPCOMP typelevel interrupt.
- CRYPTOCELL typelevel interrupt.
- EGU0 typelevel interrupt.
- EGU1 typelevel interrupt.
- EGU2 typelevel interrupt.
- EGU3 typelevel interrupt.
- EGU4 typelevel interrupt.
- EGU5 typelevel interrupt.
- FPU typelevel interrupt.
- GPIOTE0 typelevel interrupt.
- GPIOTE1 typelevel interrupt.
- I2S0 typelevel interrupt.
- IPC typelevel interrupt.
- KMU typelevel interrupt.
- NFCT typelevel interrupt.
- PDM0 typelevel interrupt.
- PWM0 typelevel interrupt.
- PWM1 typelevel interrupt.
- PWM2 typelevel interrupt.
- PWM3 typelevel interrupt.
- QDEC0 typelevel interrupt.
- QDEC1 typelevel interrupt.
- QSPI typelevel interrupt.
- RTC0 typelevel interrupt.
- RTC1 typelevel interrupt.
- SAADC typelevel interrupt.
- SERIAL0 typelevel interrupt.
- SERIAL1 typelevel interrupt.
- SERIAL2 typelevel interrupt.
- SERIAL3 typelevel interrupt.
- SPIM4 typelevel interrupt.
- SPU typelevel interrupt.
- TIMER0 typelevel interrupt.
- TIMER1 typelevel interrupt.
- TIMER2 typelevel interrupt.
- USBD typelevel interrupt.
- USBREGULATOR typelevel interrupt.
- WDT0 typelevel interrupt.
- WDT1 typelevel interrupt.
Traits§
- Compile-time assertion that an interrupt has been bound to a handler.
- Interrupt handler trait.
- Type-level interrupt.