Module sqspi 

Soft Quad Serial Peripheral Interface (sQSPI) flash driver.

sQSPI is a QSPI/SPI controller implemented in firmware running on the nRF54L’s FLPR RISC-V coprocessor (VPR00). Unlike a hardware peripheral its register interface lives in shared RAM, not at a fixed MMIO address: the host CPU and the FLPR communicate through a “virtual register block” (see the [regs] submodule) that the firmware emulates as if it were a real QSPI peripheral.

This driver exposes the same API shape as the hardware [crate::qspi] driver (the same read/write/erase methods, blocking variants, custom_instruction, and the embedded-storage NorFlash traits), with two extra constructor arguments specific to a soft peripheral:

• firmware: the FLPR firmware blob (starts with a metadata header). The caller owns and provides it (e.g. via include_bytes!).
• ram: a RAM buffer the firmware code, its working RAM, and the virtual register block are placed into.

Example

use embassy_nrf::sqspi::{self, Config};
use static_cell::ConstStaticCell;
use core::mem::MaybeUninit;

bind_interrupts!(struct Irqs { VPR00 => sqspi::InterruptHandler<peripherals::VPR>; });

static FW: &[u8] = include_bytes!("sqspi_firmware.bin");
static RAM: ConstStaticCell<[MaybeUninit<u8>; 0x4000]> = ConstStaticCell::new([MaybeUninit::uninit(); 0x4000]);
let ram = RAM.take();

let mut config = Config::default();
config.capacity = 8 * 1024 * 1024;
let mut q = sqspi::Sqspi::new(
    p.VPR, Irqs, FW, ram,
    p.P2_01, p.P2_05, p.P2_02, p.P2_04, p.P2_03, p.P2_00, config,
).unwrap();

Structs

Config

sQSPI driver configuration.

InterruptHandler

Interrupt handler for the sQSPI driver.

Mode

SPI mode

Sqspi

sQSPI flash driver.

Enums

AddressMode

Flash addressing mode.

Error

sQSPI error.

Frequency

sQSPI bus frequency.

Lines

Multi-line SPI mode for the address and data phases.

Phase

Clock phase

Polarity

Clock polarity

Constants

MODE_0

Helper for CPOL = 0, CPHA = 0

MODE_3

Helper for CPOL = 1, CPHA = 1

Traits

Instance

sQSPI peripheral instance (the VPR coprocessor running the firmware).