Module regs 

Structs

Clkselect

Master clock generator configuration

Ctrl

Aditional PDM configurability

Enable

PDM module enable register

Gainl

Left output gain adjustment

Gainr

Right output gain adjustment

Hpdisable

High pass filter disable

Hppole

Settings for the high-pass filter

Int

Enable or disable interrupt

Maxcnt

Number of bytes to allocate memory for in EasyDMA mode

Mode

Defines the routing of the connected PDM microphone signals

Prescaler

The prescaler is used to set the PDM frequency

Ratio

Selects the decimation ratio between PDM_CLK and output sample rate. When RATIO is selected to be ‘custom’, the decimation rate should be set using the FILTER.CTRL field before setting the RATIO to 7 Change PRESCALER.DIVISOR accordingly.

Sampledelay

Input Data Sampling with Number of ckFilterL (double frequency of PDM_CLK) Clock Cycle Delay. Optionally,input sample point can be delayed independently on left and right channels using FILTER:CTRL[20:19] bits

Softcycles

Soft mute settings

Softmute

Soft mute function

Terminateonbuserror

Terminate the transaction if a BUSERROR event is detected.