Module regs
- Align
- Alignment of sample within the audio data word.
- ConfigMode
- Mode configuration
- Delay
- Set channel delay.
- Duration
- Set FSYNC duration.
- En
- Master clock generator enable.
- Enable
- Enable TDM
- FsyncPolarity
- Set FSYNC Polarity.
- Int
- Enable or disable interrupt
- Mask
- Select which channels are to be used.
- MckDiv
- MCK divider.
- MckSrc
- MCK clock source selection
- Num
- Select number of channels.
- RxdAmount
- Number of bytes transferred in the last transaction, updated after the END event.
- RxdCurrentamount
- Number of bytes transferred in the current transaction
- RxdMaxcnt
- Maximum number of bytes in channel buffer
- RxdMode
- Configure EasyDMA mode
- RxdTerminateonbuserror
- Terminate the transaction if a BUSERROR event is detected.
- Rxtxen
- Reception (RX) and transmission (TX) enable.
- SckDiv
- SCK divider.
- SckPolarity
- Set SCK Polarity.
- SckSrc
- SCK clock source selection
- Swidth
- Sample and word width configuration.
- TxdAmount
- Number of bytes transferred in the last transaction, updated after the END event.
- TxdCurrentamount
- Number of bytes transferred in the current transaction
- TxdMaxcnt
- Maximum number of bytes in channel buffer
- TxdMode
- Configure EasyDMA mode
- TxdTerminateonbuserror
- Terminate the transaction if a BUSERROR event is detected.