Structsยง
- Authstatus
- Indicates the current level of tracing permitted by the system
- Claimclr
- Software can use the claim tag to coordinate application and debugger access to trace unit functionality. The claim tags have no effect on the operation of the component. The CLAIMCLR register sets the bits in the claim tag to 0 and determines the current value of the claim tag.
- Claimset
- Software can use the claim tag to coordinate application and debugger access to trace unit functionality. The claim tags have no effect on the operation of the component. The CLAIMSET register sets bits in the claim tag, and determines the number of claim bits implemented.
- Devid
- Indicates the capabilities of the component.
- Devtype
- The DEVTYPE register provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information.
- Idfilter0
- The IDFILTER0 register enables the programming of ID filtering for master port 0.
- Idfilter1
- The IDFILTER1 register enables the programming of ID filtering for master port 1.
- Itatbctr0
- The ITATBCTR0 register controls the value of the atvalidm0, atvalidm1, and atreadys outputs in integration mode.
- Itatbctr1
- The ITATBCTR1 register returns the value of the atreadym0, atreadym1, and atvalids inputs in integration mode.
- Itctrl
- The ITCTRL register enables the component to switch from a functional mode, which is the default behavior, to integration mode where the inputs and outputs of the component can be directly controlled for the purposes of integration testing and topology detection.
- Lar
- This is used to enable write access to device registers.
- Lsr
- This indicates the status of the lock control mechanism. This lock prevents accidental writes by code under debug. Accesses to the extended stimulus port registers are not affected by the lock mechanism. This register must always be present although there might not be any lock access control mechanism. The lock mechanism, where present and locked, must block write accesses to any control register, except the Lock Access Register. For most components this covers all registers except for the Lock Access Register.