Structsยง
- Cs
- ADC Control and Status
- Div
- Clock divider. If non-zero, CS_START_MANY will start conversions at regular intervals rather than back-to-back. The divider is reset when either of these fields are written. Total period is 1 + INT + FRAC / 256
- Fcs
- FIFO control and status
- Fifo
- Conversion result FIFO
- Int
- Interrupt status after masking & forcing
- Result
- Result of most recent ADC conversion