Structs§
- DivCsr
- Control and status register for divider.
- FifoSt
- Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.
- Interp0accum0add
- Values written here are atomically added to ACCUM0 Reading yields lane 0’s raw shift and mask value (BASE0 not added).
- Interp0accum1add
- Values written here are atomically added to ACCUM1 Reading yields lane 1’s raw shift and mask value (BASE1 not added).
- Interp0ctrl
Lane0 - Control register for lane 0
- Interp0ctrl
Lane1 - Control register for lane 1
- Interp1accum0add
- Values written here are atomically added to ACCUM0 Reading yields lane 0’s raw shift and mask value (BASE0 not added).
- Interp1accum1add
- Values written here are atomically added to ACCUM1 Reading yields lane 1’s raw shift and mask value (BASE1 not added).
- Interp1ctrl
Lane0 - Control register for lane 0
- Interp1ctrl
Lane1 - Control register for lane 1