Module regs
Source - Cpsr
- Clock prescale register, SSPCPSR on page 3-8
- Cr0
- Control register 0, SSPCR0 on page 3-4
- Cr1
- Control register 1, SSPCR1 on page 3-5
- Dmacr
- DMA control register, SSPDMACR on page 3-12
- Dr
- Data register, SSPDR on page 3-6
- Icr
- Interrupt clear register, SSPICR on page 3-11
- Imsc
- Interrupt mask set or clear register, SSPIMSC on page 3-9
- Mis
- Masked interrupt status register, SSPMIS on page 3-11
- Pcellid0
- PrimeCell identification registers, SSPPCellID0-3 on page 3-16
- Pcellid1
- PrimeCell identification registers, SSPPCellID0-3 on page 3-16
- Pcellid2
- PrimeCell identification registers, SSPPCellID0-3 on page 3-16
- Pcellid3
- PrimeCell identification registers, SSPPCellID0-3 on page 3-16
- Periphid0
- Peripheral identification registers, SSPPeriphID0-3 on page 3-13
- Periphid1
- Peripheral identification registers, SSPPeriphID0-3 on page 3-13
- Periphid2
- Peripheral identification registers, SSPPeriphID0-3 on page 3-13
- Periphid3
- Peripheral identification registers, SSPPeriphID0-3 on page 3-13
- Ris
- Raw interrupt status register, SSPRIS on page 3-10
- Sr
- Status register, SSPSR on page 3-7