Control PD pins to memories. Set high to put memories to a low power state. In this state the memories will retain contents but not be accessible Use with caution
For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you’re feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 32…47. USB GPIO 56..57 QSPI GPIO 58..63