Module rp_pac::clocks::regs

Structs

• ClkAdcCtrl
  Clock control, can be changed on-the-fly (except for auxsrc)
• ClkAdcDiv
  Clock divisor, can be changed on-the-fly
• ClkGpoutCtrl
  Clock control, can be changed on-the-fly (except for auxsrc)
• ClkGpoutDiv
  Clock divisor, can be changed on-the-fly
• ClkPeriCtrl
  Clock control, can be changed on-the-fly (except for auxsrc)
• ClkRefCtrl
  Clock control, can be changed on-the-fly (except for auxsrc)
• ClkRefDiv
  Clock divisor, can be changed on-the-fly
• ClkRtcCtrl
  Clock control, can be changed on-the-fly (except for auxsrc)
• ClkRtcDiv
  Clock divisor, can be changed on-the-fly
• ClkSysCtrl
  Clock control, can be changed on-the-fly (except for auxsrc)
• ClkSysDiv
  Clock divisor, can be changed on-the-fly
• ClkSysResusCtrl
• ClkSysResusStatus
• ClkUsbCtrl
  Clock control, can be changed on-the-fly (except for auxsrc)
• ClkUsbDiv
  Clock divisor, can be changed on-the-fly
• Enabled0
  indicates the state of the clock enable
• Enabled1
  indicates the state of the clock enable
• Fc0delay
  Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period
• Fc0interval
  The test interval is 0.98us * 2interval, but let’s call it 1us * 2interval The default gives a test interval of 250us
• Fc0maxKhz
  Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags
• Fc0minKhz
  Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags
• Fc0refKhz
  Reference clock frequency in kHz
• Fc0result
  Result of frequency measurement, only valid when status_done=1
• Fc0src
  Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count
• Fc0status
  Frequency counter status
• Int
  Interrupt Force
• SleepEn0
  enable clock in sleep mode
• SleepEn1
  enable clock in sleep mode
• WakeEn0
  enable clock in wake mode
• WakeEn1
  enable clock in wake mode