Embassy
rp-pac

Crates

git

Versions

default

Flavors

Module rp_pac::spi::regs

source ·

Structs

  • Clock prescale register, SSPCPSR on page 3-8
  • Control register 0, SSPCR0 on page 3-4
  • Control register 1, SSPCR1 on page 3-5
  • DMA control register, SSPDMACR on page 3-12
  • Data register, SSPDR on page 3-6
  • Interrupt clear register, SSPICR on page 3-11
  • Interrupt mask set or clear register, SSPIMSC on page 3-9
  • Masked interrupt status register, SSPMIS on page 3-11
  • PrimeCell identification registers, SSPPCellID0-3 on page 3-16
  • PrimeCell identification registers, SSPPCellID0-3 on page 3-16
  • PrimeCell identification registers, SSPPCellID0-3 on page 3-16
  • PrimeCell identification registers, SSPPCellID0-3 on page 3-16
  • Peripheral identification registers, SSPPeriphID0-3 on page 3-13
  • Peripheral identification registers, SSPPeriphID0-3 on page 3-13
  • Peripheral identification registers, SSPPeriphID0-3 on page 3-13
  • Peripheral identification registers, SSPPeriphID0-3 on page 3-13
  • Raw interrupt status register, SSPRIS on page 3-10
  • Status register, SSPSR on page 3-7