Module regs

Structs

Ahb1enr

AHB1 peripheral clock enable register

Ahb1rstr

AHB1 peripheral reset register

Ahb1smenr

AHB1 peripheral clocks enable in Sleep and Stop modes register

Ahb2enr

AHB2 peripheral clock enable register

Ahb2rstr

AHB2 peripheral reset register

Ahb2smenr

AHB2 peripheral clocks enable in Sleep and Stop modes register

Ahb3enr

AHB3 peripheral clock enable register

Ahb3rstr

AHB3 peripheral reset register

Ahb3smenr

AHB3 peripheral clocks enable in Sleep and Stop modes register

Apb1enr1

APB1ENR1

Apb1enr2

APB1 peripheral clock enable register 2

Apb1rstr1

APB1 peripheral reset register 1

Apb1rstr2

APB1 peripheral reset register 2

Apb1smenr1

APB1SMENR1

Apb1smenr2

APB1 peripheral clocks enable in Sleep and Stop modes register 2

Apb2enr

APB2ENR

Apb2rstr

APB2 peripheral reset register

Apb2smenr

APB2SMENR

Bdcr

BDCR

Ccipr

CCIPR

Ccipr2

Peripherals independent clock configuration register

Cfgr

Clock configuration register

Cicr

Clock interrupt clear register

Cier

Clock interrupt enable register

Cifr

Clock interrupt flag register

Cr

Clock control register

Crrcr

Clock recovery RC register

Csr

CSR

Icscr

Internal clock sources calibration register

Pllcfgr

PLL configuration register