Module regs

Structs

Ahbenr

AHB peripheral clock enable register.

Ahbrstr

AHB peripheral reset register.

Ahbsmenr

AHB peripheral clock enable in Sleep/Stop mode register.

Apbenr1

APB peripheral clock enable register 1.

Apbenr2

APB peripheral clock enable register 2.

Apbrstr1

APB peripheral reset register 1.

Apbrstr2

APB peripheral reset register 2.

Apbsmenr1

APB peripheral clock enable in Sleep/Stop mode register 1.

Apbsmenr2

APB peripheral clock enable in Sleep/Stop mode register 2.

Bdcr

RTC domain control register.

Ccipr

Peripherals independent clock configuration register.

Cfgr

Clock configuration register.

Cicr

Clock interrupt clear register.

Cier

Clock interrupt enable register.

Cifr

Clock interrupt flag register.

Cr

Clock control register.

Crrcr

RCC clock recovery RC register.

Csr

Control/status register.

Dbgcfgr

Debug configuration register.

Gpioenr

I/O port clock enable register.

Gpiorstr

I/O port reset register.

Gpiosmenr

I/O port in Sleep mode clock enable register.

Icscr

Internal clock sources calibration register.

Pllcfgr

PLL configuration register.