Module regs

Structs

Btr

bit timing register

Esr

interrupt enable register

Fa1r

filter activation register

Ffa1r

filter FIFO assignment register

Fm1r

filter mode register

Fmr

filter master register

Fr1

Filter bank 0 register 1

Fr2

Filter bank 0 register 2

Fs1r

filter scale register

Ier

interrupt enable register

Mcr

master control register

Msr

master status register

Rdhr

receive FIFO mailbox data high register

Rdlr

mailbox data high register

Rdtr

mailbox data high register

Rfr

receive FIFO 0 register

Rir

receive FIFO mailbox identifier register

Tdhr

mailbox data high register

Tdlr

mailbox data low register

Tdtr

mailbox data length control and time stamp register

Tir

TX mailbox identifier register

Tsr

transmit status register