pub struct Config {
pub enable_in_doze_mode: bool,
pub calibration_average_mode: CalAvgs,
pub power_pre_enabled: bool,
pub power_up_delay: u8,
pub reference_voltage_source: ReferenceVoltage,
pub power_level_mode: Pwrsel,
pub trigger_priority_policy: TriggerPriorityPolicy,
pub conv_pause_delay: Option<u16>,
pub power: PoweredClock,
pub source: AdcClockSel,
pub div: Div4,
}Expand description
Configuration for the LPADC peripheral.
Fields§
§enable_in_doze_mode: boolControl system transition to Stop and Wait power modes while ADC is converting.
When enabled in Doze mode, immediate entries to Wait or Stop are allowed.
When disabled, the ADC will wait for the current averaging iteration/FIFO storage to complete before acknowledging stop or wait mode entry.
calibration_average_mode: CalAvgsAuto-Calibration Averages.
power_pre_enabled: boolWhen true, the ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption).
power_up_delay: u8Power-up delay value (in ADC clock cycles)
reference_voltage_source: ReferenceVoltageReference voltage source selection
power_level_mode: PwrselPower configuration selection.
trigger_priority_policy: TriggerPriorityPolicyTrigger priority policy for handling multiple triggers
conv_pause_delay: Option<u16>Controls the duration of pausing during command execution sequencing. The pause delay is a count of (convPauseDelay*4) ADCK cycles.
The available value range is in 9-bit. When None, the pausing function is not enabled
power: PoweredClockPower configuration (normal/deep sleep behavior)
source: AdcClockSelADC clock source selection
div: Div4Clock divider for ADC clock