Enum SpllMode 

#[non_exhaustive]
pub enum SpllMode {
    Mode1a {
        m_mult: u16,
    },
    Mode1b {
        m_mult: u16,
        p_div: u8,
        bypass_p2_div: bool,
    },
    Mode1c {
        m_mult: u16,
        n_div: u8,
    },
    Mode1d {
        m_mult: u16,
        n_div: u8,
        p_div: u8,
        bypass_p2_div: bool,
    },
}

Mode of operation for the SPLL/PLL1

NOTE: Currently, only “Mode 1” normal operational modes are implemented, as described in the Reference Manual.

Variants (Non-exhaustive)

Non-exhaustive enums could have additional variants added in future. Therefore, when matching against variants of non-exhaustive enums, an extra wildcard arm must be added to account for any future variants.

Mode1a

Mode 1a does not use the Pre/Post dividers.

Fout = m_mult x SpllSource

Both of the following constraints must be met:

• Fout: 275MHz to 550MHz
• Fout: 4.3MHz to 2x Max CPU Frequency

Fields

m_mult: u16

PLL Multiplier. Must be in the range 1..=65535.

Mode1b

Mode 1b does not use the Pre-divider.

• if !bypass_p2_div: Fout = (M / (2 x P)) x Fin
• if bypass_p2_div: Fout = (M / P ) x Fin

Both of the following constraints must be met:

• Fcco: 275MHz to 550MHz
  • Fcco = m_mult x SpllSource
• Fout: 4.3MHz to 2x Max CPU Frequency

Fields

m_mult: u16

PLL Multiplier. m_mult must be in the range 1..=65535.

p_div: u8

Post Divider. p_div must be in the range 1..=31.

bypass_p2_div: bool

Bonus post divider

Mode1c

Mode 1c does use the Pre-divider, but does not use the Post-divider

Fout = (M / N) x Fin

Both of the following constraints must be met:

• Fout: 275MHz to 550MHz
• Fout: 4.3MHz to 2x Max CPU Frequency

Fields

m_mult: u16

PLL Multiplier. m_mult must be in the range 1..=65535.

n_div: u8

Pre Divider. n_div must be in the range 1..=255.

Mode1d

Mode 1b uses both the Pre and Post dividers.

• if !bypass_p2_div: Fout = (M / (N x 2 x P)) x Fin
• if bypass_p2_div: Fout = (M / ( N x P )) x Fin

Both of the following constraints must be met:

• Fcco: 275MHz to 550MHz
  • Fcco = (m_mult x SpllSource) / (n_div x p_div (x 2))
• Fout: 4.3MHz to 2x Max CPU Frequency

Fields

m_mult: u16

PLL Multiplier. m_mult must be in the range 1..=65535.

n_div: u8

Pre Divider. n_div must be in the range 1..=255.

p_div: u8

Post Divider. p_div must be in the range 1..=31.

bypass_p2_div: bool

Bonus post divider