Enum LpuartClockSel 

pub enum LpuartClockSel {
    FroLfDiv,
    FroHfDiv,
    ClkIn,
    Clk16K,
    Clk1M,
    Pll1ClkDiv,
    None,
}

Selectable clocks for Lpuart peripherals

Variants

FroLfDiv

FRO12M/FRO_LF/SIRC clock source, passed through divider “fro_lf_div”

FroHfDiv

FRO180M/FRO_HF/FIRC clock source, passed through divider “fro_hf_div”

ClkIn

SOSC/XTAL/EXTAL clock source

Clk16K

FRO16K/clk_16k source

Clk1M

clk_1m/FRO_LF divided by 12

Pll1ClkDiv

Output of PLL1, passed through clock divider, “pll1_clk_div”, maybe “pll1_lf_div”?

None

Disabled

Trait Implementations

impl Clone for LpuartClockSel

fn clone(&self) -> LpuartClockSel

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for LpuartClockSel

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Copy for LpuartClockSel