#[non_exhaustive]pub struct Clocks {Show 14 fields
pub clk_in: Option<Clock>,
pub fro_hf_root: Option<Clock>,
pub fro_hf: Option<Clock>,
pub clk_45m: Option<Clock>,
pub fro_hf_div: Option<Clock>,
pub fro_12m_root: Option<Clock>,
pub fro_12m: Option<Clock>,
pub clk_1m: Option<Clock>,
pub fro_lf_div: Option<Clock>,
pub clk_16k_vsys: Option<Clock>,
pub clk_16k_vdd_core: Option<Clock>,
pub main_clk: Option<Clock>,
pub cpu_system_clk: Option<Clock>,
pub pll1_clk: Option<Clock>,
}Expand description
The Clocks structure contains the initialized state of the core system clocks
These values are configured by providing config::ClocksConfig to the init() function
at boot time.
Fields (Non-exhaustive)§
This struct is marked as non-exhaustive
Struct { .. } syntax; cannot be matched against without a wildcard ..; and struct update syntax will not work.clk_in: Option<Clock>The clk_in is a clock provided by an external oscillator
fro_hf_root: Option<Clock>fro_hf_root is the direct output of the FRO180M internal oscillator
It is used to feed downstream clocks, such as fro_hf, clk_45m,
and fro_hf_div.
fro_hf: Option<Clock>fro_hf is the same frequency as fro_hf_root, but behind a gate.
clk_45m: Option<Clock>clk_45 is a 45MHz clock, sourced from fro_hf.
fro_hf_div: Option<Clock>fro_hf_div is a configurable frequency clock, sourced from fro_hf.
fro_12m_root: Option<Clock>fro_12m_root is the direct output of the FRO12M internal oscillator
It is used to feed downstream clocks, such as fro_12m, clk_1m,
and fro_lf_div`.
fro_12m: Option<Clock>fro_12m is the same frequency as fro_12m_root, but behind a gate.
clk_1m: Option<Clock>clk_1m is a 1MHz clock, sourced from fro_12m
fro_lf_div: Option<Clock>fro_lf_div is a configurable frequency clock, sourced from fro_12m
clk_16k_vsys: Option<Clock>clk_16k_vsys is one of two outputs of the FRO16K internal oscillator.
Also referred to as clk_16k[0] in the datasheet, it feeds peripherals in
the system domain, such as the CMP and RTC.
clk_16k_vdd_core: Option<Clock>clk_16k_vdd_core is one of two outputs of the FRO16K internal oscillator.
Also referred to as clk_16k[1] in the datasheet, it feeds peripherals in
the VDD Core domain, such as the OSTimer or LPUarts.
main_clk: Option<Clock>main_clk is the main clock used by the CPU, AHB, APB, IPS bus, and some
peripherals.
cpu_system_clk: Option<Clock>CPU_CLK or SYSTEM_CLK is the output of main_clk, run through the AHBCLKDIV
pll1_clk: Option<Clock>pll1_clk is the output of the main system PLL, pll1.
Implementations§
Source§impl Clocks
The Clocks type’s methods generally take the form of “ensure X clock is active”.
impl Clocks
The Clocks type’s methods generally take the form of “ensure X clock is active”.
These methods are intended to be used by HAL peripheral implementors to ensure that their
selected clocks are active at a suitable level at time of construction. These methods
return the frequency of the requested clock, in Hertz, or a ClockError.
Sourcepub fn ensure_fro_lf_div_active(
&self,
at_level: &PoweredClock,
) -> Result<u32, ClockError>
pub fn ensure_fro_lf_div_active( &self, at_level: &PoweredClock, ) -> Result<u32, ClockError>
Ensure the fro_lf_div clock is active and valid at the given power state.
Sourcepub fn ensure_fro_hf_active(
&self,
at_level: &PoweredClock,
) -> Result<u32, ClockError>
pub fn ensure_fro_hf_active( &self, at_level: &PoweredClock, ) -> Result<u32, ClockError>
Ensure the fro_hf clock is active and valid at the given power state.
Sourcepub fn ensure_fro_hf_div_active(
&self,
at_level: &PoweredClock,
) -> Result<u32, ClockError>
pub fn ensure_fro_hf_div_active( &self, at_level: &PoweredClock, ) -> Result<u32, ClockError>
Ensure the fro_hf_div clock is active and valid at the given power state.
Sourcepub fn ensure_clk_in_active(
&self,
_at_level: &PoweredClock,
) -> Result<u32, ClockError>
pub fn ensure_clk_in_active( &self, _at_level: &PoweredClock, ) -> Result<u32, ClockError>
Ensure the clk_in clock is active and valid at the given power state.
Sourcepub fn ensure_clk_16k_vsys_active(
&self,
_at_level: &PoweredClock,
) -> Result<u32, ClockError>
pub fn ensure_clk_16k_vsys_active( &self, _at_level: &PoweredClock, ) -> Result<u32, ClockError>
Ensure the clk_16k_vsys clock is active and valid at the given power state.
Sourcepub fn ensure_clk_16k_vdd_core_active(
&self,
_at_level: &PoweredClock,
) -> Result<u32, ClockError>
pub fn ensure_clk_16k_vdd_core_active( &self, _at_level: &PoweredClock, ) -> Result<u32, ClockError>
Ensure the clk_16k_vdd_core clock is active and valid at the given power state.
Sourcepub fn ensure_clk_1m_active(
&self,
at_level: &PoweredClock,
) -> Result<u32, ClockError>
pub fn ensure_clk_1m_active( &self, at_level: &PoweredClock, ) -> Result<u32, ClockError>
Ensure the clk_1m clock is active and valid at the given power state.
Sourcepub fn ensure_pll1_clk_active(
&self,
_at_level: &PoweredClock,
) -> Result<u32, ClockError>
pub fn ensure_pll1_clk_active( &self, _at_level: &PoweredClock, ) -> Result<u32, ClockError>
Ensure the pll1_clk clock is active and valid at the given power state.
Sourcepub fn ensure_pll1_clk_div_active(
&self,
_at_level: &PoweredClock,
) -> Result<u32, ClockError>
pub fn ensure_pll1_clk_div_active( &self, _at_level: &PoweredClock, ) -> Result<u32, ClockError>
Ensure the pll1_clk_div clock is active and valid at the given power state.
Sourcepub fn ensure_cpu_system_clk_active(
&self,
at_level: &PoweredClock,
) -> Result<u32, ClockError>
pub fn ensure_cpu_system_clk_active( &self, at_level: &PoweredClock, ) -> Result<u32, ClockError>
Ensure the CPU_CLK or SYSTEM_CLK is active