Module regs

Structs

• Enable
  PDM module enable register
• Gainl
  Left output gain adjustment
• Gainr
  Right output gain adjustment
• Int
  Enable or disable interrupt
• Maxcnt
  Number of samples to allocate memory for in EasyDMA mode
• Mclkconfig
  Master clock generator configuration
• Mode
  Defines the routing of the connected PDM microphones’ signals
• Pdmclkctrl
  PDM clock generator control
• Ratio
  Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly.