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Module regs

Module regs 

Structsยง

Config
Configuration register.
Csndur
Minimum duration between edge of CSN and edge of SCK. When SHORTS.END_START is used, this is also the minimum duration CSN must stay high between transactions.
Csnpol
Polarity of CSN output.
Dcxcnt
DCX configuration.
Enable
Enable SPIM.
Frequency
SPI frequency. Accuracy depends on the HFCLK source selected.
Int
Disable interrupt.
Orc
Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT.
RxdAmount
Number of bytes transferred in the last transaction.
RxdList
EasyDMA list type.
RxdMaxcnt
Maximum number of bytes in receive buffer.
Rxdelay
Sample delay for input serial data on MISO.
Shorts
Shortcuts between local events and tasks.
Stallstat
Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU.
TxdAmount
Number of bytes transferred in the last transaction.
TxdList
EasyDMA list type.
TxdMaxcnt
Number of bytes in transmit buffer.