Struct Pll

pub struct Pll {
    pub source: PllSource,
    pub prediv_m: PllM,
    pub mul_n: PllN,
    pub div_p: Option<PllP>,
    pub div_q: Option<PllQ>,
    pub div_r: Option<PllR>,
}

PLL Configuration

Use this struct to configure the PLL source, input frequency, multiplication factor, and output dividers. Be sure to keep check the datasheet for your specific part for the appropriate frequency ranges for each of these settings.

Fields

source: PllSource

PLL Source clock selection.

prediv_m: PllM

PLL pre-divider

mul_n: PllN

PLL multiplication factor for VCO

div_p: Option<PllP>

PLL division factor for P clock (ADC Clock)

div_q: Option<PllQ>

PLL division factor for Q clock (USB, I2S23, SAI1, FDCAN, QSPI)

div_r: Option<PllR>

PLL division factor for R clock (SYSCLK)