Struct PllConfig

pub struct PllConfig {
    pub source: PllSource,
    pub m: Pllm,
    pub n: Plln,
    pub p: Plldiv,
    pub q: Plldiv,
    pub r: Plldiv,
}

Fields

source: PllSource

The clock source for the PLL.

m: Pllm

The PLL prescaler.

The clock speed of the source divided by m must be between 4 and 16 MHz.

n: Plln

The PLL multiplier.

The multiplied clock – source divided by m times n – must be between 128 and 544 MHz. The upper limit may be lower depending on the Config { voltage_range }.

p: Plldiv

The divider for the P output.

The P output is one of several options that can be used to feed the SAI/MDF/ADF Clock mux’s.

q: Plldiv

The divider for the Q output.

The Q ouput is one of severals options that can be used to feed the 48MHz clocks and the OCTOSPI clock. It may also be used on the MDF/ADF clock mux’s.

r: Plldiv

The divider for the R output.

When used to drive the system clock, source divided by m times n divided by r must not exceed 160 MHz. System clocks above 55 MHz require a non-default Config { voltage_range }.

Implementations

impl PllConfig

pub const fn hsi_160mhz() -> Self

A configuration for HSI / 1 * 10 / 1 = 160 MHz

pub const fn msis_160mhz() -> Self

A configuration for MSIS @ 48 MHz / 3 * 10 / 1 = 160 MHz

Trait Implementations

impl Clone for PllConfig

fn clone(&self) -> PllConfig

Returns a duplicate of the value.

const fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for PllConfig