Module regs

Structs

Endianness

This register defines the endianness of the Host-accessible registers, and can only be written once.

HostBoot

Hardware configuration of the CRYPTOCELL subsystem. Reset value holds the supported features.

HostCryptokeySel

AES hardware key select.

HostIotKdr0

This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained.

HostIotKprtlLock

This write-once register is the K_PRTL lock register. When this register is set, K_PRTL cannot be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain.

HostIotLcs

Controls life-cycle state (LCS) for CRYPTOCELL subsystem

Icr

Interrupt clear register. Writing a 1 bit into a field in this register will clear the corresponding bit in IRR.

Imr

Interrupt mask register. Each bit of this register holds the mask of a single interrupt source.

Irr

Interrupt request register. Each bit of this register holds the interrupt status of a single interrupt source. If corresponding IMR bit is unmasked, an interrupt is generated.