Status register for AES engine activity.
Writing to this address triggers the AES engine to generate K1 and K2 for AES-CMAC operations.
Writing to this address triggers the AES engine to perform a CMAC operation with size 0. The CMAC result can be read from the AES_IV_0 register.
Control the AES engine behavior.
This register enables the AES CTR no increment mode in which the counter mode is not incremented between two blocks
Hardware configuration of the AES engine. Reset value holds the supported features.
Writing to this address trigger sampling of the HW key to the AES_KEY_0 register
Reset the AES engine.