Specifies the number of bytes the CPU will write to the DIN_BUFFER, ensuring the cryptographic engine processes the correct amount of data.
Status register for DIN DMA engine activity when accessing memory.
Status register for DIN DMA engine activity when accessing RNG SRAM.
Configure the endianness of DIN DMA transactions towards RNG SRAM.
Register indicating if DIN FIFO is empty and if more data can be accepted.
Reset the DIN FIFO, effectively clearing the FIFO for new data.
Reset the DIN DMA engine.
Indicates that the next CPU write to the DIN_BUFFER is the last in the sequence. This is needed only when the data size is NOT modulo 4 (e.g. HASH padding).
The number of bytes to be read from memory. Writing to this register triggers the DMA operation.