Configuration register
Minimum duration between edge of CSN and edge of SCK at the start and the end of a transaction, and minimum duration CSN will stay high between transactions if END-START shortcut is used
Polarity of CSN output
DCX configuration
Enable SPIM
SPI frequency. Accuracy depends on the HFCLK source selected.
Disable interrupt
Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT
Number of bytes transferred in the last transaction
EasyDMA list type
Maximum number of bytes in receive buffer
Sample delay for input serial data on MISO
Shortcuts between local events and tasks
Stall status for EasyDMA RAM accesses. The fields in this register are set to STALL by hardware whenever a stall occurs and can be cleared (set to NOSTALL) by the CPU.
Number of bytes transferred in the last transaction
EasyDMA list type
Number of bytes in transmit buffer