Master clock generator configuration
Aditional PDM configurability
PDM module enable register
Left output gain adjustment
Right output gain adjustment
High pass filter disable
Settings for the high-pass filter
Enable or disable interrupt
Number of bytes to allocate memory for in EasyDMA mode
Defines the routing of the connected PDM microphone signals
The prescaler is used to set the PDM frequency
Selects the decimation ratio between PDM_CLK and output sample rate. When RATIO is selected to be ‘custom’, the decimation rate should be set using the FILTER.CTRL field before setting the RATIO to 7 Change PRESCALER.DIVISOR accordingly.
Input Data Sampling with Number of ckFilterL (double frequency of PDM_CLK) Clock Cycle Delay. Optionally,input sample point can be delayed independently on left and right channels using FILTER:CTRL[20:19] bits
Soft mute settings
Soft mute function
Terminate the transaction if a BUSERROR event is detected.