Alignment of sample within the audio data word.
Mode configuration
Set channel delay.
Set FSYNC duration.
Master clock generator enable.
Enable TDM
Set FSYNC Polarity.
Enable or disable interrupt
Select which channels are to be used.
MCK divider.
MCK clock source selection
Select number of channels.
Number of bytes transferred in the last transaction, updated after the END event.
Number of bytes transferred in the current transaction
Maximum number of bytes in channel buffer
Configure EasyDMA mode
Terminate the transaction if a BUSERROR event is detected.
Reception (RX) and transmission (TX) enable.
SCK divider.
Set SCK Polarity.
SCK clock source selection
Sample and word width configuration.
Number of bytes transferred in the last transaction, updated after the END event.
Number of bytes transferred in the current transaction
Maximum number of bytes in channel buffer
Configure EasyDMA mode
Terminate the transaction if a BUSERROR event is detected.