Struct Clocks

pub struct Clocks(pub *mut u8);

Tuple Fields

0: *mut u8

Implementations

impl Clocks

pub fn clk_gpout0_ctrl(self) -> Reg<ClkGpout0ctrl, RW>

Clock control, can be changed on-the-fly (except for auxsrc)

pub fn clk_gpout0_div(self) -> Reg<ClkGpout0div, RW>

Clock divisor, can be changed on-the-fly

pub fn clk_gpout0_selected(self) -> Reg<u32, R>

Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

pub fn clk_gpout1_ctrl(self) -> Reg<ClkGpout1ctrl, RW>

Clock control, can be changed on-the-fly (except for auxsrc)

pub fn clk_gpout1_div(self) -> Reg<ClkGpout1div, RW>

Clock divisor, can be changed on-the-fly

pub fn clk_gpout1_selected(self) -> Reg<u32, R>

Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

pub fn clk_gpout2_ctrl(self) -> Reg<ClkGpout2ctrl, RW>

Clock control, can be changed on-the-fly (except for auxsrc)

pub fn clk_gpout2_div(self) -> Reg<ClkGpout2div, RW>

Clock divisor, can be changed on-the-fly

pub fn clk_gpout2_selected(self) -> Reg<u32, R>

Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

pub fn clk_gpout3_ctrl(self) -> Reg<ClkGpout3ctrl, RW>

Clock control, can be changed on-the-fly (except for auxsrc)

pub fn clk_gpout3_div(self) -> Reg<ClkGpout3div, RW>

Clock divisor, can be changed on-the-fly

pub fn clk_gpout3_selected(self) -> Reg<u32, R>

Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

pub fn clk_ref_ctrl(self) -> Reg<ClkRefCtrl, RW>

Clock control, can be changed on-the-fly (except for auxsrc)

pub fn clk_ref_div(self) -> Reg<ClkRefDiv, RW>

Clock divisor, can be changed on-the-fly

pub fn clk_ref_selected(self) -> Reg<u32, R>

Indicates which SRC is currently selected by the glitchless mux (one-hot). The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.

pub fn clk_sys_ctrl(self) -> Reg<ClkSysCtrl, RW>

Clock control, can be changed on-the-fly (except for auxsrc)

pub fn clk_sys_div(self) -> Reg<ClkSysDiv, RW>

Clock divisor, can be changed on-the-fly

pub fn clk_sys_selected(self) -> Reg<u32, R>

Indicates which SRC is currently selected by the glitchless mux (one-hot). The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.

pub fn clk_peri_ctrl(self) -> Reg<ClkPeriCtrl, RW>

Clock control, can be changed on-the-fly (except for auxsrc)

pub fn clk_peri_selected(self) -> Reg<u32, R>

Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

pub fn clk_usb_ctrl(self) -> Reg<ClkUsbCtrl, RW>

Clock control, can be changed on-the-fly (except for auxsrc)

pub fn clk_usb_div(self) -> Reg<ClkUsbDiv, RW>

Clock divisor, can be changed on-the-fly

pub fn clk_usb_selected(self) -> Reg<u32, R>

Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

pub fn clk_adc_ctrl(self) -> Reg<ClkAdcCtrl, RW>

Clock control, can be changed on-the-fly (except for auxsrc)

pub fn clk_adc_div(self) -> Reg<ClkAdcDiv, RW>

Clock divisor, can be changed on-the-fly

pub fn clk_adc_selected(self) -> Reg<u32, R>

Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

pub fn clk_rtc_ctrl(self) -> Reg<ClkRtcCtrl, RW>

Clock control, can be changed on-the-fly (except for auxsrc)

pub fn clk_rtc_div(self) -> Reg<ClkRtcDiv, RW>

Clock divisor, can be changed on-the-fly

pub fn clk_rtc_selected(self) -> Reg<u32, R>

Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

pub fn clk_sys_resus_ctrl(self) -> Reg<ClkSysResusCtrl, RW>

pub fn clk_sys_resus_status(self) -> Reg<ClkSysResusStatus, RW>

pub fn fc0_ref_khz(self) -> Reg<Fc0refKhz, RW>

Reference clock frequency in kHz

pub fn fc0_min_khz(self) -> Reg<Fc0minKhz, RW>

Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags

pub fn fc0_max_khz(self) -> Reg<Fc0maxKhz, RW>

Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags

pub fn fc0_delay(self) -> Reg<Fc0delay, RW>

Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period

pub fn fc0_interval(self) -> Reg<Fc0interval, RW>

The test interval is 0.98us * 2interval, but let’s call it 1us * 2interval The default gives a test interval of 250us

pub fn fc0_src(self) -> Reg<Fc0src, RW>

Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count

pub fn fc0_status(self) -> Reg<Fc0status, RW>

Frequency counter status

pub fn fc0_result(self) -> Reg<Fc0result, RW>

Result of frequency measurement, only valid when status_done=1

pub fn wake_en0(self) -> Reg<WakeEn0, RW>

enable clock in wake mode

pub fn wake_en1(self) -> Reg<WakeEn1, RW>

enable clock in wake mode

pub fn sleep_en0(self) -> Reg<SleepEn0, RW>

enable clock in sleep mode

pub fn sleep_en1(self) -> Reg<SleepEn1, RW>

enable clock in sleep mode

pub fn enabled0(self) -> Reg<Enabled0, RW>

indicates the state of the clock enable

pub fn enabled1(self) -> Reg<Enabled1, RW>

indicates the state of the clock enable

pub fn intr(self) -> Reg<Int, RW>

Raw Interrupts

pub fn inte(self) -> Reg<Int, RW>

Interrupt Enable

pub fn intf(self) -> Reg<Int, RW>

Interrupt Force

pub fn ints(self) -> Reg<Int, RW>

Interrupt status after masking & forcing

Trait Implementations

impl Clone for Clocks

fn clone(&self) -> Clocks

Returns a duplicate of the value.

const fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for Clocks

fn eq(&self, other: &Clocks) -> bool

Tests for self and other values to be equal, and is used by ==.

const fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Clocks

impl Eq for Clocks

impl Send for Clocks

impl StructuralPartialEq for Clocks

impl Sync for Clocks