pub struct Syscfg(pub *mut u8);
Expand description
Register block for various chip control signals
Tuple Fields§
§0: *mut u8
Implementations§
Source§impl Syscfg
impl Syscfg
Sourcepub fn proc0_nmi_mask(self) -> Reg<u32, RW>
pub fn proc0_nmi_mask(self) -> Reg<u32, RW>
Processor core 0 NMI source mask Set a bit high to enable NMI from that IRQ
Sourcepub fn proc1_nmi_mask(self) -> Reg<u32, RW>
pub fn proc1_nmi_mask(self) -> Reg<u32, RW>
Processor core 1 NMI source mask Set a bit high to enable NMI from that IRQ
Sourcepub fn proc_config(self) -> Reg<ProcConfig, RW>
pub fn proc_config(self) -> Reg<ProcConfig, RW>
Configuration for processors
Sourcepub fn proc_in_sync_bypass(self) -> Reg<ProcInSyncBypass, RW>
pub fn proc_in_sync_bypass(self) -> Reg<ProcInSyncBypass, RW>
For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you’re feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 0…29.
Sourcepub fn proc_in_sync_bypass_hi(self) -> Reg<ProcInSyncBypassHi, RW>
pub fn proc_in_sync_bypass_hi(self) -> Reg<ProcInSyncBypassHi, RW>
For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you’re feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 30…35 (the QSPI IOs).
Sourcepub fn dbgforce(self) -> Reg<Dbgforce, RW>
pub fn dbgforce(self) -> Reg<Dbgforce, RW>
Directly control the SWD debug port of either processor
Sourcepub fn mempowerdown(self) -> Reg<Mempowerdown, RW>
pub fn mempowerdown(self) -> Reg<Mempowerdown, RW>
Control power downs to memories. Set high to power down memories. Use with extreme caution