pub struct Channel { /* private fields */ }Implementations§
Source§impl Channel
impl Channel
pub const unsafe fn from_ptr(ptr: *mut ()) -> Self
pub const fn as_ptr(&self) -> *mut ()
Sourcepub const fn read_addr(self) -> Reg<u32, RW>
pub const fn read_addr(self) -> Reg<u32, RW>
DMA Channel 8 Read Address pointer This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
Sourcepub const fn write_addr(self) -> Reg<u32, RW>
pub const fn write_addr(self) -> Reg<u32, RW>
DMA Channel 8 Write Address pointer This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
Sourcepub const fn trans_count(self) -> Reg<u32, RW>
pub const fn trans_count(self) -> Reg<u32, RW>
DMA Channel 8 Transfer Count Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE). When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes. Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write. The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
Sourcepub const fn al1_read_addr(self) -> Reg<u32, RW>
pub const fn al1_read_addr(self) -> Reg<u32, RW>
Alias for channel 8 READ_ADDR register
Sourcepub const fn al1_write_addr(self) -> Reg<u32, RW>
pub const fn al1_write_addr(self) -> Reg<u32, RW>
Alias for channel 8 WRITE_ADDR register
Sourcepub const fn al1_trans_count_trig(self) -> Reg<u32, RW>
pub const fn al1_trans_count_trig(self) -> Reg<u32, RW>
Alias for channel 8 TRANS_COUNT register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel.
Sourcepub const fn al2_trans_count(self) -> Reg<u32, RW>
pub const fn al2_trans_count(self) -> Reg<u32, RW>
Alias for channel 8 TRANS_COUNT register
Sourcepub const fn al2_read_addr(self) -> Reg<u32, RW>
pub const fn al2_read_addr(self) -> Reg<u32, RW>
Alias for channel 8 READ_ADDR register
Sourcepub const fn al2_write_addr_trig(self) -> Reg<u32, RW>
pub const fn al2_write_addr_trig(self) -> Reg<u32, RW>
Alias for channel 8 WRITE_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel.
Sourcepub const fn al3_write_addr(self) -> Reg<u32, RW>
pub const fn al3_write_addr(self) -> Reg<u32, RW>
Alias for channel 8 WRITE_ADDR register
Sourcepub const fn al3_trans_count(self) -> Reg<u32, RW>
pub const fn al3_trans_count(self) -> Reg<u32, RW>
Alias for channel 8 TRANS_COUNT register
Sourcepub const fn al3_read_addr_trig(self) -> Reg<u32, RW>
pub const fn al3_read_addr_trig(self) -> Reg<u32, RW>
Alias for channel 8 READ_ADDR register This is a trigger register (0xc). Writing a nonzero value will reload the channel counter and start the channel.
Sourcepub const fn dbg_ctdreq(self) -> Reg<DbgCtdreq, RW>
pub const fn dbg_ctdreq(self) -> Reg<DbgCtdreq, RW>
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.