Struct rp_pac::clocks::Clocks

pub struct Clocks { /* private fields */ }

Implementations

impl Clocks

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn clk_gpout_ctrl(self, n: usize) -> Reg<ClkGpoutCtrl, RW>

Clock control, can be changed on-the-fly (except for auxsrc)

pub const fn clk_gpout_div(self, n: usize) -> Reg<ClkGpoutDiv, RW>

Clock divisor, can be changed on-the-fly

pub const fn clk_gpout_selected(self, n: usize) -> Reg<u32, R>

Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

pub const fn clk_ref_ctrl(self) -> Reg<ClkRefCtrl, RW>

Clock control, can be changed on-the-fly (except for auxsrc)

pub const fn clk_ref_div(self) -> Reg<ClkRefDiv, RW>

Clock divisor, can be changed on-the-fly

pub const fn clk_ref_selected(self) -> Reg<u32, R>

Indicates which SRC is currently selected by the glitchless mux (one-hot). The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.

pub const fn clk_sys_ctrl(self) -> Reg<ClkSysCtrl, RW>

Clock control, can be changed on-the-fly (except for auxsrc)

pub const fn clk_sys_div(self) -> Reg<ClkSysDiv, RW>

Clock divisor, can be changed on-the-fly

pub const fn clk_sys_selected(self) -> Reg<u32, R>

Indicates which SRC is currently selected by the glitchless mux (one-hot). The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.

pub const fn clk_peri_ctrl(self) -> Reg<ClkPeriCtrl, RW>

Clock control, can be changed on-the-fly (except for auxsrc)

pub const fn clk_peri_selected(self) -> Reg<u32, R>

Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

pub const fn clk_usb_ctrl(self) -> Reg<ClkUsbCtrl, RW>

Clock control, can be changed on-the-fly (except for auxsrc)

pub const fn clk_usb_div(self) -> Reg<ClkUsbDiv, RW>

Clock divisor, can be changed on-the-fly

pub const fn clk_usb_selected(self) -> Reg<u32, R>

Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

pub const fn clk_adc_ctrl(self) -> Reg<ClkAdcCtrl, RW>

Clock control, can be changed on-the-fly (except for auxsrc)

pub const fn clk_adc_div(self) -> Reg<ClkAdcDiv, RW>

Clock divisor, can be changed on-the-fly

pub const fn clk_adc_selected(self) -> Reg<u32, R>

Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

pub const fn clk_rtc_ctrl(self) -> Reg<ClkRtcCtrl, RW>

Clock control, can be changed on-the-fly (except for auxsrc)

pub const fn clk_rtc_div(self) -> Reg<ClkRtcDiv, RW>

Clock divisor, can be changed on-the-fly

pub const fn clk_rtc_selected(self) -> Reg<u32, R>

Indicates which SRC is currently selected by the glitchless mux (one-hot). This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.

pub const fn clk_sys_resus_ctrl(self) -> Reg<ClkSysResusCtrl, RW>

pub const fn clk_sys_resus_status(self) -> Reg<ClkSysResusStatus, RW>

pub const fn fc0_ref_khz(self) -> Reg<Fc0refKhz, RW>

Reference clock frequency in kHz

pub const fn fc0_min_khz(self) -> Reg<Fc0minKhz, RW>

Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags

pub const fn fc0_max_khz(self) -> Reg<Fc0maxKhz, RW>

Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags

pub const fn fc0_delay(self) -> Reg<Fc0delay, RW>

Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period

pub const fn fc0_interval(self) -> Reg<Fc0interval, RW>

The test interval is 0.98us * 2interval, but let’s call it 1us * 2interval The default gives a test interval of 250us

pub const fn fc0_src(self) -> Reg<Fc0src, RW>

Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count

pub const fn fc0_status(self) -> Reg<Fc0status, RW>

Frequency counter status

pub const fn fc0_result(self) -> Reg<Fc0result, RW>

Result of frequency measurement, only valid when status_done=1

pub const fn wake_en0(self) -> Reg<WakeEn0, RW>

enable clock in wake mode

pub const fn wake_en1(self) -> Reg<WakeEn1, RW>

enable clock in wake mode

pub const fn sleep_en0(self) -> Reg<SleepEn0, RW>

enable clock in sleep mode

pub const fn sleep_en1(self) -> Reg<SleepEn1, RW>

enable clock in sleep mode

pub const fn enabled0(self) -> Reg<Enabled0, RW>

indicates the state of the clock enable

pub const fn enabled1(self) -> Reg<Enabled1, RW>

indicates the state of the clock enable

pub const fn intr(self) -> Reg<Int, RW>

Raw Interrupts

pub const fn inte(self) -> Reg<Int, RW>

Interrupt Enable

pub const fn intf(self) -> Reg<Int, RW>

Interrupt Force

pub const fn ints(self) -> Reg<Int, RW>

Interrupt status after masking & forcing

Trait Implementations

impl Clone for Clocks

fn clone(&self) -> Clocks

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq<Clocks> for Clocks

fn eq(&self, other: &Clocks) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Clocks

impl Eq for Clocks

impl Send for Clocks

impl StructuralEq for Clocks

impl StructuralPartialEq for Clocks

impl Sync for Clocks