pub struct Dma { /* private fields */ }
Expand description
DMA with separate read and write masters
Implementations§
source§impl Dma
impl Dma
pub const unsafe fn from_ptr(ptr: *mut ()) -> Self
pub const fn as_ptr(&self) -> *mut ()
pub const fn ch(self, n: usize) -> Channel
sourcepub const fn timer(self, n: usize) -> Reg<Timer, RW>
pub const fn timer(self, n: usize) -> Reg<Timer, RW>
Pacing (X/Y) Fractional Timer The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
sourcepub const fn multi_chan_trigger(self) -> Reg<MultiChanTrigger, RW>
pub const fn multi_chan_trigger(self) -> Reg<MultiChanTrigger, RW>
Trigger one or more channels simultaneously
sourcepub const fn sniff_ctrl(self) -> Reg<SniffCtrl, RW>
pub const fn sniff_ctrl(self) -> Reg<SniffCtrl, RW>
Sniffer Control
sourcepub const fn sniff_data(self) -> Reg<u32, RW>
pub const fn sniff_data(self) -> Reg<u32, RW>
Data accumulator for sniff hardware Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.
sourcepub const fn fifo_levels(self) -> Reg<FifoLevels, RW>
pub const fn fifo_levels(self) -> Reg<FifoLevels, RW>
Debug RAF, WAF, TDF levels
sourcepub const fn chan_abort(self) -> Reg<ChanAbort, RW>
pub const fn chan_abort(self) -> Reg<ChanAbort, RW>
Abort an in-progress transfer sequence on one or more channels
sourcepub const fn n_channels(self) -> Reg<Nchannels, RW>
pub const fn n_channels(self) -> Reg<Nchannels, RW>
The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.