Struct rp_pac::i2c::regs::IcSsSclHcnt

#[repr(transparent)]
pub struct IcSsSclHcnt(pub u32);

Standard Speed I2C Clock SCL High Count Register

Tuple Fields

0: u32

Implementations

impl IcSsSclHcnt

pub const fn ic_ss_scl_hcnt(&self) -> u16

This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to ‘IC_CLK Frequency Configuration’. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10.

pub fn set_ic_ss_scl_hcnt(&mut self, val: u16)

This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to ‘IC_CLK Frequency Configuration’. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10.

Trait Implementations

impl Clone for IcSsSclHcnt

fn clone(&self) -> IcSsSclHcnt

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for IcSsSclHcnt

fn default() -> IcSsSclHcnt

Returns the “default value” for a type.

impl PartialEq<IcSsSclHcnt> for IcSsSclHcnt

fn eq(&self, other: &IcSsSclHcnt) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for IcSsSclHcnt

impl Eq for IcSsSclHcnt

impl StructuralEq for IcSsSclHcnt

impl StructuralPartialEq for IcSsSclHcnt