Struct rp_pac::sio::regs::Interp0ctrlLane0

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#[repr(transparent)]
pub struct Interp0ctrlLane0(pub u32);

Expand description

Control register for lane 0

Tuple Fields§

§0: u32

Implementations§

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impl Interp0ctrlLane0

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pub const fn shift(&self) -> u8

Logical right-shift applied to accumulator before masking

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pub fn set_shift(&mut self, val: u8)

Logical right-shift applied to accumulator before masking

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pub const fn mask_lsb(&self) -> u8

The least-significant bit allowed to pass by the mask (inclusive)

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pub fn set_mask_lsb(&mut self, val: u8)

The least-significant bit allowed to pass by the mask (inclusive)

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pub const fn mask_msb(&self) -> u8

The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out

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pub fn set_mask_msb(&mut self, val: u8)

The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out

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pub const fn signed(&self) -> bool

If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.

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pub fn set_signed(&mut self, val: bool)

If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.

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pub const fn cross_input(&self) -> bool

If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

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pub fn set_cross_input(&mut self, val: bool)

If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)

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pub const fn cross_result(&self) -> bool

If 1, feed the opposite lane’s result into this lane’s accumulator on POP.

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pub fn set_cross_result(&mut self, val: bool)

If 1, feed the opposite lane’s result into this lane’s accumulator on POP.

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pub const fn add_raw(&self) -> bool

If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.

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pub fn set_add_raw(&mut self, val: bool)

If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.

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pub const fn force_msb(&self) -> u8

ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM.

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pub fn set_force_msb(&mut self, val: u8)

ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM.

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pub const fn blend(&self) -> bool

Only present on INTERP0 on each core. If BLEND mode is enabled: - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsigned.

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pub fn set_blend(&mut self, val: bool)

Only present on INTERP0 on each core. If BLEND mode is enabled: - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsigned.

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