Struct rp_pac::sio::regs::Interp0ctrlLane1
source · #[repr(transparent)]pub struct Interp0ctrlLane1(pub u32);Expand description
Control register for lane 1
Tuple Fields§
§0: u32Implementations§
source§impl Interp0ctrlLane1
impl Interp0ctrlLane1
sourcepub const fn mask_lsb(&self) -> u8
pub const fn mask_lsb(&self) -> u8
The least-significant bit allowed to pass by the mask (inclusive)
sourcepub fn set_mask_lsb(&mut self, val: u8)
pub fn set_mask_lsb(&mut self, val: u8)
The least-significant bit allowed to pass by the mask (inclusive)
sourcepub const fn mask_msb(&self) -> u8
pub const fn mask_msb(&self) -> u8
The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out
sourcepub fn set_mask_msb(&mut self, val: u8)
pub fn set_mask_msb(&mut self, val: u8)
The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out
sourcepub const fn signed(&self) -> bool
pub const fn signed(&self) -> bool
If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.
sourcepub fn set_signed(&mut self, val: bool)
pub fn set_signed(&mut self, val: bool)
If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.
sourcepub const fn cross_input(&self) -> bool
pub const fn cross_input(&self) -> bool
If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)
sourcepub fn set_cross_input(&mut self, val: bool)
pub fn set_cross_input(&mut self, val: bool)
If 1, feed the opposite lane’s accumulator into this lane’s shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)
sourcepub const fn cross_result(&self) -> bool
pub const fn cross_result(&self) -> bool
If 1, feed the opposite lane’s result into this lane’s accumulator on POP.
sourcepub fn set_cross_result(&mut self, val: bool)
pub fn set_cross_result(&mut self, val: bool)
If 1, feed the opposite lane’s result into this lane’s accumulator on POP.
sourcepub const fn add_raw(&self) -> bool
pub const fn add_raw(&self) -> bool
If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.
sourcepub fn set_add_raw(&mut self, val: bool)
pub fn set_add_raw(&mut self, val: bool)
If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.
sourcepub const fn force_msb(&self) -> u8
pub const fn force_msb(&self) -> u8
ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM.
sourcepub fn set_force_msb(&mut self, val: u8)
pub fn set_force_msb(&mut self, val: u8)
ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM.
Trait Implementations§
source§impl Clone for Interp0ctrlLane1
impl Clone for Interp0ctrlLane1
source§fn clone(&self) -> Interp0ctrlLane1
fn clone(&self) -> Interp0ctrlLane1
1.0.0 · source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read moresource§impl Default for Interp0ctrlLane1
impl Default for Interp0ctrlLane1
source§fn default() -> Interp0ctrlLane1
fn default() -> Interp0ctrlLane1
source§impl PartialEq<Interp0ctrlLane1> for Interp0ctrlLane1
impl PartialEq<Interp0ctrlLane1> for Interp0ctrlLane1
source§fn eq(&self, other: &Interp0ctrlLane1) -> bool
fn eq(&self, other: &Interp0ctrlLane1) -> bool
self and other values to be equal, and is used
by ==.