#[repr(transparent)]pub struct Ctrl(pub u32);Expand description
Cache control
Tuple Fields§
§0: u32Implementations§
source§impl Ctrl
impl Ctrl
sourcepub const fn en(&self) -> bool
pub const fn en(&self) -> bool
When 1, enable the cache. When the cache is disabled, all XIP accesses will go straight to the flash, without querying the cache. When enabled, cacheable XIP accesses will query the cache, and the flash will not be accessed if the tag matches and the valid bit is set. If the cache is enabled, cache-as-SRAM accesses have no effect on the cache data RAM, and will produce a bus error response.
sourcepub fn set_en(&mut self, val: bool)
pub fn set_en(&mut self, val: bool)
When 1, enable the cache. When the cache is disabled, all XIP accesses will go straight to the flash, without querying the cache. When enabled, cacheable XIP accesses will query the cache, and the flash will not be accessed if the tag matches and the valid bit is set. If the cache is enabled, cache-as-SRAM accesses have no effect on the cache data RAM, and will produce a bus error response.
sourcepub const fn err_badwrite(&self) -> bool
pub const fn err_badwrite(&self) -> bool
When 1, writes to any alias other than 0x0 (caching, allocating) will produce a bus fault. When 0, these writes are silently ignored. In either case, writes to the 0x0 alias will deallocate on tag match, as usual.
sourcepub fn set_err_badwrite(&mut self, val: bool)
pub fn set_err_badwrite(&mut self, val: bool)
When 1, writes to any alias other than 0x0 (caching, allocating) will produce a bus fault. When 0, these writes are silently ignored. In either case, writes to the 0x0 alias will deallocate on tag match, as usual.
sourcepub const fn power_down(&self) -> bool
pub const fn power_down(&self) -> bool
When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot be enabled when powered down. Cache-as-SRAM accesses will produce a bus error response when the cache is powered down.
sourcepub fn set_power_down(&mut self, val: bool)
pub fn set_power_down(&mut self, val: bool)
When 1, the cache memories are powered down. They retain state, but can not be accessed. This reduces static power dissipation. Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot be enabled when powered down. Cache-as-SRAM accesses will produce a bus error response when the cache is powered down.