Struct Fdcan

pub struct Fdcan { /* private fields */ }

Expand description

FDCAN

Implementations§

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impl Fdcan

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn crel(self) -> Reg<Crel, R>

FDCAN Core Release Register

pub const fn endn(self) -> Reg<Endn, R>

FDCAN Core Release Register

pub const fn dbtp(self) -> Reg<Dbtp, RW>

This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.

pub const fn test(self) -> Reg<Test, RW>

Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus.

pub const fn rwd(self) -> Reg<Rwd, RW>

The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock.

pub const fn cccr(self) -> Reg<Cccr, RW>

For details about setting and resetting of single bits see Software initialization.

pub const fn nbtp(self) -> Reg<Nbtp, RW>

FDCAN_NBTP

pub const fn tscc(self) -> Reg<Tscc, RW>

FDCAN Timestamp Counter Configuration Register

pub const fn tscv(self) -> Reg<Tscv, RW>

FDCAN Timestamp Counter Value Register

pub const fn tocc(self) -> Reg<Tocc, RW>

FDCAN Timeout Counter Configuration Register

pub const fn tocv(self) -> Reg<Tocv, RW>

FDCAN Timeout Counter Value Register

pub const fn ecr(self) -> Reg<Ecr, R>

FDCAN Error Counter Register

pub const fn psr(self) -> Reg<Psr, RW>

FDCAN Protocol Status Register

pub const fn tdcr(self) -> Reg<Tdcr, RW>

FDCAN Transmitter Delay Compensation Register

pub const fn ir(self) -> Reg<Ir, RW>

The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled.

pub const fn ie(self) -> Reg<Ie, RW>

The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line.

pub const fn ils(self) -> Reg<Ils, RW>

The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1].

pub const fn ile(self) -> Reg<Ile, RW>

Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1.

pub const fn rxgfc(self) -> Reg<Rxgfc, RW>

Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path.

pub const fn xidam(self) -> Reg<Xidam, RW>

FDCAN Extended ID and Mask Register

pub const fn hpms(self) -> Reg<Hpms, R>

This register is updated every time a Message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages.

pub const fn rxfs(self, n: usize) -> Reg<Rxfs, R>

FDCAN Rx FIFO X Status Register

pub const fn rxfa(self, n: usize) -> Reg<Rxfa, RW>

CAN Rx FIFO 0 Acknowledge Register

pub const fn txbc(self) -> Reg<Txbc, RW>

FDCAN Tx Buffer Configuration Register

pub const fn txfqs(self) -> Reg<Txfqs, R>

The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated).