Enum Cckdiv
#[repr(u8)]pub enum Cckdiv {
Show 16 variants
DIV1 = 0,
DIV2 = 1,
DIV3 = 2,
DIV4 = 3,
DIV5 = 4,
DIV6 = 5,
DIV7 = 6,
DIV8 = 7,
DIV9 = 8,
DIV10 = 9,
DIV11 = 10,
DIV12 = 11,
DIV13 = 12,
DIV14 = 13,
DIV15 = 14,
DIV16 = 15,
}
Expand description
Divider to control the CCK clock. This bit is set and reset by software. It is used to control the frequency of the bitstream clock on the CCK pin.
Variants§
DIV1 = 0
The ADF_CCK clock is adf_proc_ck.
DIV2 = 1
The ADF_CCK clock is adf_proc_ck divided by 2.
DIV3 = 2
The ADF_CCK clock is adf_proc_ck divided by 3.
DIV4 = 3
The ADF_CCK clock is adf_proc_ck divided by 4.
DIV5 = 4
The ADF_CCK clock is adf_proc_ck divided by 5.
DIV6 = 5
The ADF_CCK clock is adf_proc_ck divided by 6.
DIV7 = 6
The ADF_CCK clock is adf_proc_ck divided by 7.
DIV8 = 7
The ADF_CCK clock is adf_proc_ck divided by 8.
DIV9 = 8
The ADF_CCK clock is adf_proc_ck divided by 9.
DIV10 = 9
The ADF_CCK clock is adf_proc_ck divided by 10.
DIV11 = 10
The ADF_CCK clock is adf_proc_ck divided by 11.
DIV12 = 11
The ADF_CCK clock is adf_proc_ck divided by 12.
DIV13 = 12
The ADF_CCK clock is adf_proc_ck divided by 13.
DIV14 = 13
The ADF_CCK clock is adf_proc_ck divided by 14.
DIV15 = 14
The ADF_CCK clock is adf_proc_ck divided by 15.
DIV16 = 15
The ADF_CCK clock is adf_proc_ck divided by 16.