Struct Apb1rstr1
#[repr(transparent)]pub struct Apb1rstr1(pub u32);Expand description
RCC APB1 peripheral reset register 1
Tuple Fields§
§0: u32Implementations§
§impl Apb1rstr1
impl Apb1rstr1
pub const fn tim2rst(&self) -> bool
pub const fn tim2rst(&self) -> bool
TIM2 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub fn set_tim2rst(&mut self, val: bool)
pub fn set_tim2rst(&mut self, val: bool)
TIM2 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub const fn tim3rst(&self) -> bool
pub const fn tim3rst(&self) -> bool
TIM3 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub fn set_tim3rst(&mut self, val: bool)
pub fn set_tim3rst(&mut self, val: bool)
TIM3 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub const fn tim4rst(&self) -> bool
pub const fn tim4rst(&self) -> bool
TIM4 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub fn set_tim4rst(&mut self, val: bool)
pub fn set_tim4rst(&mut self, val: bool)
TIM4 reset Set and cleared by software. Access can be secured by GTZC_TZSC TIM4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub const fn spi2rst(&self) -> bool
pub const fn spi2rst(&self) -> bool
SPI2 reset Set and cleared by software. Access can be secured by GTZC_TZSC SPI2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub fn set_spi2rst(&mut self, val: bool)
pub fn set_spi2rst(&mut self, val: bool)
SPI2 reset Set and cleared by software. Access can be secured by GTZC_TZSC SPI2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub const fn usart2rst(&self) -> bool
pub const fn usart2rst(&self) -> bool
USART2 reset Set and cleared by software. Access can be secured by GTZC_TZSC UART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub fn set_usart2rst(&mut self, val: bool)
pub fn set_usart2rst(&mut self, val: bool)
USART2 reset Set and cleared by software. Access can be secured by GTZC_TZSC UART2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub const fn usart3rst(&self) -> bool
pub const fn usart3rst(&self) -> bool
USART3 reset Set and cleared by software. Access can be secured by GTZC_TZSC UART3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub fn set_usart3rst(&mut self, val: bool)
pub fn set_usart3rst(&mut self, val: bool)
USART3 reset Set and cleared by software. Access can be secured by GTZC_TZSC UART3SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub const fn i2c1rst(&self) -> bool
pub const fn i2c1rst(&self) -> bool
I2C1 reset Set and cleared by software. Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub fn set_i2c1rst(&mut self, val: bool)
pub fn set_i2c1rst(&mut self, val: bool)
I2C1 reset Set and cleared by software. Access can be secured by GTZC_TZSC I2C1SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub const fn i2c2rst(&self) -> bool
pub const fn i2c2rst(&self) -> bool
I2C2 reset Set and cleared by software. Access can be secured by GTZC_TZSC I2C2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub fn set_i2c2rst(&mut self, val: bool)
pub fn set_i2c2rst(&mut self, val: bool)
I2C2 reset Set and cleared by software. Access can be secured by GTZC_TZSC I2C2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.