Struct Apb1enr2
#[repr(transparent)]pub struct Apb1enr2(pub u32);Expand description
RCC APB1 peripheral clock enable register 2
Tuple Fields§
§0: u32Implementations§
§impl Apb1enr2
impl Apb1enr2
pub const fn i2c4en(&self) -> bool
pub const fn i2c4en(&self) -> bool
I2C4 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC I2C4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub fn set_i2c4en(&mut self, val: bool)
pub fn set_i2c4en(&mut self, val: bool)
I2C4 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC I2C4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub const fn lptim2en(&self) -> bool
pub const fn lptim2en(&self) -> bool
LPTIM2 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub fn set_lptim2en(&mut self, val: bool)
pub fn set_lptim2en(&mut self, val: bool)
LPTIM2 bus and kernel clocks enable Set and cleared by software. Access can be secured by GTZC_TZSC LPTIM2SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.