Struct Pll3cfgr
#[repr(transparent)]pub struct Pll3cfgr(pub u32);Expand description
RCC PLL3 configuration register
Tuple Fields§
§0: u32Implementations§
§impl Pll3cfgr
impl Pll3cfgr
pub const fn pllsrc(&self) -> Pllsrc
pub const fn pllsrc(&self) -> Pllsrc
PLL3 entry clock source Set and cleared by software to select PLL3 clock source. These bits can be written only when the PLL3 is disabled. In order to save power, when no PLL3 is used, the value of PLL3SRC must be 00.
pub fn set_pllsrc(&mut self, val: Pllsrc)
pub fn set_pllsrc(&mut self, val: Pllsrc)
PLL3 entry clock source Set and cleared by software to select PLL3 clock source. These bits can be written only when the PLL3 is disabled. In order to save power, when no PLL3 is used, the value of PLL3SRC must be 00.
pub const fn pllrge(&self) -> Pllrge
pub const fn pllrge(&self) -> Pllrge
PLL3 input frequency range Set and reset by software to select the proper reference frequency range used for PLL3. This bit must be written before enabling the PLL3. 00-01-10: PLL3 input (ref3_ck) clock range frequency between 4 and 8 MHz
pub fn set_pllrge(&mut self, val: Pllrge)
pub fn set_pllrge(&mut self, val: Pllrge)
PLL3 input frequency range Set and reset by software to select the proper reference frequency range used for PLL3. This bit must be written before enabling the PLL3. 00-01-10: PLL3 input (ref3_ck) clock range frequency between 4 and 8 MHz
pub const fn pllfracen(&self) -> bool
pub const fn pllfracen(&self) -> bool
PLL3 fractional latch enable Set and reset by software to latch the content of PLL3FRACN into the ΣΠmodulator. In order to latch the PLL3FRACN value into the ΣΠmodulator, PLL3FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL3FRACN into the modulator (see for details).
pub fn set_pllfracen(&mut self, val: bool)
pub fn set_pllfracen(&mut self, val: bool)
PLL3 fractional latch enable Set and reset by software to latch the content of PLL3FRACN into the ΣΠmodulator. In order to latch the PLL3FRACN value into the ΣΠmodulator, PLL3FRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLL3FRACN into the modulator (see for details).
pub const fn pllm(&self) -> Pllm
pub const fn pllm(&self) -> Pllm
Prescaler for PLL3 Set and cleared by software to configure the prescaler of the PLL3. The VCO3 input frequency is PLL3 input clock frequency/PLL3M. This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). …
pub fn set_pllm(&mut self, val: Pllm)
pub fn set_pllm(&mut self, val: Pllm)
Prescaler for PLL3 Set and cleared by software to configure the prescaler of the PLL3. The VCO3 input frequency is PLL3 input clock frequency/PLL3M. This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0). …
pub const fn pllpen(&self) -> bool
pub const fn pllpen(&self) -> bool
PLL3 DIVP divider output enable Set and reset by software to enable the pll3_p_ck output of the PLL3. To save power, PLL3PEN and PLL3P bits must be set to 0 when the pll3_p_ck is not used. This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).
pub fn set_pllpen(&mut self, val: bool)
pub fn set_pllpen(&mut self, val: bool)
PLL3 DIVP divider output enable Set and reset by software to enable the pll3_p_ck output of the PLL3. To save power, PLL3PEN and PLL3P bits must be set to 0 when the pll3_p_ck is not used. This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).
pub fn pllqen(&self, n: usize) -> bool
pub fn pllqen(&self, n: usize) -> bool
PLL3 DIVQ divider output enable Set and reset by software to enable the pll3_q_ck output of the PLL3. To save power, PLL3QEN and PLL3Q bits must be set to 0 when the pll3_q_ck is not used. This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).
pub fn set_pllqen(&mut self, n: usize, val: bool)
pub fn set_pllqen(&mut self, n: usize, val: bool)
PLL3 DIVQ divider output enable Set and reset by software to enable the pll3_q_ck output of the PLL3. To save power, PLL3QEN and PLL3Q bits must be set to 0 when the pll3_q_ck is not used. This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).
pub const fn pllren(&self) -> bool
pub const fn pllren(&self) -> bool
PLL3 DIVR divider output enable Set and reset by software to enable the pll3_r_ck output of the PLL3. To save power, PLL3REN and PLL3R bits must be set to 0 when the pll3_r_ck is not used. This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).
pub fn set_pllren(&mut self, val: bool)
pub fn set_pllren(&mut self, val: bool)
PLL3 DIVR divider output enable Set and reset by software to enable the pll3_r_ck output of the PLL3. To save power, PLL3REN and PLL3R bits must be set to 0 when the pll3_r_ck is not used. This bit can be written only when the PLL3 is disabled (PLL3ON = 0 and PLL3RDY = 0).