Enum stm32_metapac::timer::vals::Urs
#[repr(u8)]pub enum Urs {
ANYEVENT = 0,
COUNTERONLY = 1,
}
Variants§
ANYEVENT = 0
Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request
COUNTERONLY = 1
Only counter overflow/underflow generates an update interrupt or DMA request
Implementations§
Trait Implementations§
§impl Ord for Urs
impl Ord for Urs
§impl PartialOrd for Urs
impl PartialOrd for Urs
impl Copy for Urs
impl Eq for Urs
impl StructuralPartialEq for Urs
Auto Trait Implementations§
impl Freeze for Urs
impl RefUnwindSafe for Urs
impl Send for Urs
impl Sync for Urs
impl Unpin for Urs
impl UnwindSafe for Urs
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more
source§impl<T> CloneToUninit for Twhere
T: Clone,
impl<T> CloneToUninit for Twhere
T: Clone,
source§unsafe fn clone_to_uninit(&self, dst: *mut T)
unsafe fn clone_to_uninit(&self, dst: *mut T)
🔬This is a nightly-only experimental API. (
clone_to_uninit
)