Enum stm32_metapac::Interrupt
pub enum Interrupt {
Show 69 variants
WWDG = 0,
TAMP_STAMP = 2,
RTC_WKUP = 3,
FLASH = 4,
RCC = 5,
EXTI0 = 6,
EXTI1 = 7,
EXTI2_TSC = 8,
EXTI3 = 9,
EXTI4 = 10,
DMA1_CHANNEL1 = 11,
DMA1_CHANNEL2 = 12,
DMA1_CHANNEL3 = 13,
DMA1_CHANNEL4 = 14,
DMA1_CHANNEL5 = 15,
DMA1_CHANNEL6 = 16,
DMA1_CHANNEL7 = 17,
ADC1_2 = 18,
CAN_TX = 19,
CAN_RX0 = 20,
CAN_RX1 = 21,
CAN_SCE = 22,
EXTI9_5 = 23,
TIM1_BRK_TIM15 = 24,
TIM1_UP_TIM16 = 25,
TIM1_TRG_COM_TIM17 = 26,
TIM1_CC = 27,
TIM2 = 28,
TIM3 = 29,
TIM4 = 30,
I2C1_EV = 31,
I2C1_ER = 32,
I2C2_EV = 33,
I2C2_ER = 34,
SPI1 = 35,
SPI2 = 36,
USART1 = 37,
USART2 = 38,
USART3 = 39,
EXTI15_10 = 40,
RTC_ALARM = 41,
TIM8_BRK = 43,
TIM8_UP = 44,
TIM8_TRG_COM = 45,
TIM8_CC = 46,
ADC3 = 47,
FMC = 48,
SPI3 = 51,
UART4 = 52,
UART5 = 53,
TIM6_DAC = 54,
TIM7 = 55,
DMA2_CHANNEL1 = 56,
DMA2_CHANNEL2 = 57,
DMA2_CHANNEL3 = 58,
DMA2_CHANNEL4 = 59,
DMA2_CHANNEL5 = 60,
ADC4 = 61,
COMP1_2_3 = 64,
COMP4_5_6 = 65,
COMP7 = 66,
I2C3_EV = 72,
I2C3_ER = 73,
TIM20_BRK = 77,
TIM20_UP = 78,
TIM20_TRG_COM = 79,
TIM20_CC = 80,
FPU = 81,
SPI4 = 84,
}
Variants§
WWDG = 0
0 - WWDG
TAMP_STAMP = 2
2 - TAMP_STAMP
RTC_WKUP = 3
3 - RTC_WKUP
FLASH = 4
4 - FLASH
RCC = 5
5 - RCC
EXTI0 = 6
6 - EXTI0
EXTI1 = 7
7 - EXTI1
EXTI2_TSC = 8
8 - EXTI2_TSC
EXTI3 = 9
9 - EXTI3
EXTI4 = 10
10 - EXTI4
DMA1_CHANNEL1 = 11
11 - DMA1_CHANNEL1
DMA1_CHANNEL2 = 12
12 - DMA1_CHANNEL2
DMA1_CHANNEL3 = 13
13 - DMA1_CHANNEL3
DMA1_CHANNEL4 = 14
14 - DMA1_CHANNEL4
DMA1_CHANNEL5 = 15
15 - DMA1_CHANNEL5
DMA1_CHANNEL6 = 16
16 - DMA1_CHANNEL6
DMA1_CHANNEL7 = 17
17 - DMA1_CHANNEL7
ADC1_2 = 18
18 - ADC1_2
CAN_TX = 19
19 - CAN_TX
CAN_RX0 = 20
20 - CAN_RX0
CAN_RX1 = 21
21 - CAN_RX1
CAN_SCE = 22
22 - CAN_SCE
EXTI9_5 = 23
23 - EXTI9_5
TIM1_BRK_TIM15 = 24
24 - TIM1_BRK_TIM15
TIM1_UP_TIM16 = 25
25 - TIM1_UP_TIM16
TIM1_TRG_COM_TIM17 = 26
26 - TIM1_TRG_COM_TIM17
TIM1_CC = 27
27 - TIM1_CC
TIM2 = 28
28 - TIM2
TIM3 = 29
29 - TIM3
TIM4 = 30
30 - TIM4
I2C1_EV = 31
31 - I2C1_EV
I2C1_ER = 32
32 - I2C1_ER
I2C2_EV = 33
33 - I2C2_EV
I2C2_ER = 34
34 - I2C2_ER
SPI1 = 35
35 - SPI1
SPI2 = 36
36 - SPI2
USART1 = 37
37 - USART1
USART2 = 38
38 - USART2
USART3 = 39
39 - USART3
EXTI15_10 = 40
40 - EXTI15_10
RTC_ALARM = 41
41 - RTC_ALARM
TIM8_BRK = 43
43 - TIM8_BRK
TIM8_UP = 44
44 - TIM8_UP
TIM8_TRG_COM = 45
45 - TIM8_TRG_COM
TIM8_CC = 46
46 - TIM8_CC
ADC3 = 47
47 - ADC3
FMC = 48
48 - FMC
SPI3 = 51
51 - SPI3
UART4 = 52
52 - UART4
UART5 = 53
53 - UART5
TIM6_DAC = 54
54 - TIM6_DAC
TIM7 = 55
55 - TIM7
DMA2_CHANNEL1 = 56
56 - DMA2_CHANNEL1
DMA2_CHANNEL2 = 57
57 - DMA2_CHANNEL2
DMA2_CHANNEL3 = 58
58 - DMA2_CHANNEL3
DMA2_CHANNEL4 = 59
59 - DMA2_CHANNEL4
DMA2_CHANNEL5 = 60
60 - DMA2_CHANNEL5
ADC4 = 61
61 - ADC4
COMP1_2_3 = 64
64 - COMP1_2_3
COMP4_5_6 = 65
65 - COMP4_5_6
COMP7 = 66
66 - COMP7
I2C3_EV = 72
72 - I2C3_EV
I2C3_ER = 73
73 - I2C3_ER
TIM20_BRK = 77
77 - TIM20_BRK
TIM20_UP = 78
78 - TIM20_UP
TIM20_TRG_COM = 79
79 - TIM20_TRG_COM
TIM20_CC = 80
80 - TIM20_CC
FPU = 81
81 - FPU
SPI4 = 84
84 - SPI4
Trait Implementations§
§impl InterruptNumber for Interrupt
impl InterruptNumber for Interrupt
impl Copy for Interrupt
impl Eq for Interrupt
impl StructuralPartialEq for Interrupt
Auto Trait Implementations§
impl Freeze for Interrupt
impl RefUnwindSafe for Interrupt
impl Send for Interrupt
impl Sync for Interrupt
impl Unpin for Interrupt
impl UnwindSafe for Interrupt
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
source§impl<T> CloneToUninit for Twhere
T: Clone,
impl<T> CloneToUninit for Twhere
T: Clone,
source§unsafe fn clone_to_uninit(&self, dst: *mut T)
unsafe fn clone_to_uninit(&self, dst: *mut T)
clone_to_uninit
)