- AHB1 peripheral clock enable register 
- AHB1 peripheral reset register 
- AHB1 peripheral clocks enable in Sleep and Stop modes register 
- AHB2 peripheral clock enable register 
- AHB2 peripheral reset register 
- AHB2 peripheral clocks enable in Sleep and Stop modes register 
- AHB3 peripheral clock enable register 
- AHB3 peripheral reset register 
- AHB3 peripheral clocks enable in Sleep and Stop modes register 
- APB1ENR1 
- APB1 peripheral clock enable register 2 
- APB1 peripheral reset register 1 
- APB1 peripheral reset register 2 
- APB1SMENR1 
- APB1 peripheral clocks enable in Sleep and Stop modes register 2 
- APB2ENR 
- APB2 peripheral reset register 
- APB2SMENR 
- BDCR 
- CCIPR 
- Peripherals independent clock configuration register 
- Clock configuration register 
- Clock interrupt clear register 
- Clock interrupt enable register 
- Clock interrupt flag register 
- Clock control register 
- Clock recovery RC register 
- CSR 
- Internal clock sources calibration register 
- PLL configuration register