Struct stm32_metapac::can::regs::Rxgfc
#[repr(transparent)]pub struct Rxgfc(pub u32);
Expand description
FDCAN global filter configuration register
Tuple Fields§
§0: u32
Implementations§
§impl Rxgfc
impl Rxgfc
pub const fn rrfe(&self) -> bool
pub const fn rrfe(&self) -> bool
Reject remote frames extended. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1
pub fn set_rrfe(&mut self, val: bool)
pub fn set_rrfe(&mut self, val: bool)
Reject remote frames extended. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1
pub const fn rrfs(&self) -> bool
pub const fn rrfs(&self) -> bool
Reject remote frames standard. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1
pub fn set_rrfs(&mut self, val: bool)
pub fn set_rrfs(&mut self, val: bool)
Reject remote frames standard. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1
pub const fn anfe(&self) -> Anfe
pub const fn anfe(&self) -> Anfe
Accept non-matching frames extended. Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1
pub fn set_anfe(&mut self, val: Anfe)
pub fn set_anfe(&mut self, val: Anfe)
Accept non-matching frames extended. Defines how received messages with 29-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1
pub const fn anfs(&self) -> Anfs
pub const fn anfs(&self) -> Anfs
Accept Non-matching frames standard. Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1
pub fn set_anfs(&mut self, val: Anfs)
pub fn set_anfs(&mut self, val: Anfs)
Accept Non-matching frames standard. Defines how received messages with 11-bit IDs that do not match any element of the filter list are treated. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1
pub const fn f1om(&self) -> bool
pub const fn f1om(&self) -> bool
FIFO 1 operation mode (overwrite or blocking). This is a protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1
pub fn set_f1om(&mut self, val: bool)
pub fn set_f1om(&mut self, val: bool)
FIFO 1 operation mode (overwrite or blocking). This is a protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1
pub const fn f0om(&self) -> bool
pub const fn f0om(&self) -> bool
FIFO 0 operation mode (overwrite or blocking). This is protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1
pub fn set_f0om(&mut self, val: bool)
pub fn set_f0om(&mut self, val: bool)
FIFO 0 operation mode (overwrite or blocking). This is protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1
pub const fn lss(&self) -> u8
pub const fn lss(&self) -> u8
List size standard. >28: Values greater than 28 are interpreted as 28. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.
pub fn set_lss(&mut self, val: u8)
pub fn set_lss(&mut self, val: u8)
List size standard. >28: Values greater than 28 are interpreted as 28. These are protected write (P) bits, which means that write access by the bits is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1.
Trait Implementations§
impl Copy for Rxgfc
impl Eq for Rxgfc
impl StructuralPartialEq for Rxgfc
Auto Trait Implementations§
impl Freeze for Rxgfc
impl RefUnwindSafe for Rxgfc
impl Send for Rxgfc
impl Sync for Rxgfc
impl Unpin for Rxgfc
impl UnwindSafe for Rxgfc
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
source§impl<T> CloneToUninit for Twhere
T: Clone,
impl<T> CloneToUninit for Twhere
T: Clone,
source§unsafe fn clone_to_uninit(&self, dst: *mut T)
unsafe fn clone_to_uninit(&self, dst: *mut T)
clone_to_uninit
)