Struct stm32_metapac::adccommon::regs::Ccr

#[repr(transparent)]
pub struct Ccr(pub u32);

common control register

Tuple Fields

0: u32

Implementations

impl Ccr

pub const fn ckmode(&self) -> Ckmode

ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

pub fn set_ckmode(&mut self, val: Ckmode)

ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0).

pub const fn presc(&self) -> Presc

ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00.

pub fn set_presc(&mut self, val: Presc)

ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00.

pub const fn vrefen(&self) -> bool

VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel

pub fn set_vrefen(&mut self, val: bool)

VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel

pub const fn tsen(&self) -> bool

VSENSE enable This bit is set and cleared by software to control VSENSE

pub fn set_tsen(&mut self, val: bool)

VSENSE enable This bit is set and cleared by software to control VSENSE

pub const fn vbaten(&self) -> bool

VBAT enable This bit is set and cleared by software to control

pub fn set_vbaten(&mut self, val: bool)

VBAT enable This bit is set and cleared by software to control

Trait Implementations

impl Clone for Ccr

fn clone(&self) -> Ccr

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Ccr

fn default() -> Ccr

Returns the “default value” for a type.

impl PartialEq for Ccr

fn eq(&self, other: &Ccr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Ccr

impl Eq for Ccr

impl StructuralPartialEq for Ccr