Enum stm32_metapac::Interrupt
pub enum Interrupt {
Show 77 variants
WWDG = 0,
PVD_AVD = 1,
RTC = 2,
TAMP = 4,
RAMCFG = 5,
FLASH = 6,
RCC = 9,
EXTI0 = 11,
EXTI1 = 12,
EXTI2 = 13,
EXTI3 = 14,
EXTI4 = 15,
EXTI5 = 16,
EXTI6 = 17,
EXTI7 = 18,
EXTI8 = 19,
EXTI9 = 20,
EXTI10 = 21,
EXTI11 = 22,
EXTI12 = 23,
EXTI13 = 24,
EXTI14 = 25,
EXTI15 = 26,
GPDMA1_CHANNEL0 = 27,
GPDMA1_CHANNEL1 = 28,
GPDMA1_CHANNEL2 = 29,
GPDMA1_CHANNEL3 = 30,
GPDMA1_CHANNEL4 = 31,
GPDMA1_CHANNEL5 = 32,
GPDMA1_CHANNEL6 = 33,
GPDMA1_CHANNEL7 = 34,
IWDG = 35,
ADC1 = 37,
DAC1 = 38,
FDCAN1_IT0 = 39,
FDCAN1_IT1 = 40,
TIM1_BRK = 41,
TIM1_UP = 42,
TIM1_TRG_COM = 43,
TIM1_CC = 44,
TIM2 = 45,
TIM3 = 46,
TIM6 = 49,
TIM7 = 50,
I2C1_EV = 51,
I2C1_ER = 52,
I2C2_EV = 53,
I2C2_ER = 54,
SPI1 = 55,
SPI2 = 56,
SPI3 = 57,
USART1 = 58,
USART2 = 59,
USART3 = 60,
LPUART1 = 63,
LPTIM1 = 64,
LPTIM2 = 70,
USB_DRD_FS = 74,
CRS = 75,
GPDMA2_CHANNEL0 = 90,
GPDMA2_CHANNEL1 = 91,
GPDMA2_CHANNEL2 = 92,
GPDMA2_CHANNEL3 = 93,
GPDMA2_CHANNEL4 = 94,
GPDMA2_CHANNEL5 = 95,
GPDMA2_CHANNEL6 = 96,
GPDMA2_CHANNEL7 = 97,
FPU = 103,
ICACHE = 104,
DTS = 113,
RNG = 114,
HASH = 117,
I3C1_EV = 123,
I3C1_ER = 124,
I3C2_EV = 131,
I3C2_ER = 132,
COMP1 = 133,
}
Variants§
WWDG = 0
0 - WWDG
PVD_AVD = 1
1 - PVD_AVD
RTC = 2
2 - RTC
TAMP = 4
4 - TAMP
RAMCFG = 5
5 - RAMCFG
FLASH = 6
6 - FLASH
RCC = 9
9 - RCC
EXTI0 = 11
11 - EXTI0
EXTI1 = 12
12 - EXTI1
EXTI2 = 13
13 - EXTI2
EXTI3 = 14
14 - EXTI3
EXTI4 = 15
15 - EXTI4
EXTI5 = 16
16 - EXTI5
EXTI6 = 17
17 - EXTI6
EXTI7 = 18
18 - EXTI7
EXTI8 = 19
19 - EXTI8
EXTI9 = 20
20 - EXTI9
EXTI10 = 21
21 - EXTI10
EXTI11 = 22
22 - EXTI11
EXTI12 = 23
23 - EXTI12
EXTI13 = 24
24 - EXTI13
EXTI14 = 25
25 - EXTI14
EXTI15 = 26
26 - EXTI15
GPDMA1_CHANNEL0 = 27
27 - GPDMA1_CHANNEL0
GPDMA1_CHANNEL1 = 28
28 - GPDMA1_CHANNEL1
GPDMA1_CHANNEL2 = 29
29 - GPDMA1_CHANNEL2
GPDMA1_CHANNEL3 = 30
30 - GPDMA1_CHANNEL3
GPDMA1_CHANNEL4 = 31
31 - GPDMA1_CHANNEL4
GPDMA1_CHANNEL5 = 32
32 - GPDMA1_CHANNEL5
GPDMA1_CHANNEL6 = 33
33 - GPDMA1_CHANNEL6
GPDMA1_CHANNEL7 = 34
34 - GPDMA1_CHANNEL7
IWDG = 35
35 - IWDG
ADC1 = 37
37 - ADC1
DAC1 = 38
38 - DAC1
FDCAN1_IT0 = 39
39 - FDCAN1_IT0
FDCAN1_IT1 = 40
40 - FDCAN1_IT1
TIM1_BRK = 41
41 - TIM1_BRK
TIM1_UP = 42
42 - TIM1_UP
TIM1_TRG_COM = 43
43 - TIM1_TRG_COM
TIM1_CC = 44
44 - TIM1_CC
TIM2 = 45
45 - TIM2
TIM3 = 46
46 - TIM3
TIM6 = 49
49 - TIM6
TIM7 = 50
50 - TIM7
I2C1_EV = 51
51 - I2C1_EV
I2C1_ER = 52
52 - I2C1_ER
I2C2_EV = 53
53 - I2C2_EV
I2C2_ER = 54
54 - I2C2_ER
SPI1 = 55
55 - SPI1
SPI2 = 56
56 - SPI2
SPI3 = 57
57 - SPI3
USART1 = 58
58 - USART1
USART2 = 59
59 - USART2
USART3 = 60
60 - USART3
LPUART1 = 63
63 - LPUART1
LPTIM1 = 64
64 - LPTIM1
LPTIM2 = 70
70 - LPTIM2
USB_DRD_FS = 74
74 - USB_DRD_FS
CRS = 75
75 - CRS
GPDMA2_CHANNEL0 = 90
90 - GPDMA2_CHANNEL0
GPDMA2_CHANNEL1 = 91
91 - GPDMA2_CHANNEL1
GPDMA2_CHANNEL2 = 92
92 - GPDMA2_CHANNEL2
GPDMA2_CHANNEL3 = 93
93 - GPDMA2_CHANNEL3
GPDMA2_CHANNEL4 = 94
94 - GPDMA2_CHANNEL4
GPDMA2_CHANNEL5 = 95
95 - GPDMA2_CHANNEL5
GPDMA2_CHANNEL6 = 96
96 - GPDMA2_CHANNEL6
GPDMA2_CHANNEL7 = 97
97 - GPDMA2_CHANNEL7
FPU = 103
103 - FPU
ICACHE = 104
104 - ICACHE
DTS = 113
113 - DTS
RNG = 114
114 - RNG
HASH = 117
117 - HASH
I3C1_EV = 123
123 - I3C1_EV
I3C1_ER = 124
124 - I3C1_ER
I3C2_EV = 131
131 - I3C2_EV
I3C2_ER = 132
132 - I3C2_ER
COMP1 = 133
133 - COMP1
Trait Implementations§
§impl InterruptNumber for Interrupt
impl InterruptNumber for Interrupt
impl Copy for Interrupt
impl Eq for Interrupt
impl StructuralPartialEq for Interrupt
Auto Trait Implementations§
impl Freeze for Interrupt
impl RefUnwindSafe for Interrupt
impl Send for Interrupt
impl Sync for Interrupt
impl Unpin for Interrupt
impl UnwindSafe for Interrupt
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
source§impl<T> CloneToUninit for Twhere
T: Clone,
impl<T> CloneToUninit for Twhere
T: Clone,
source§unsafe fn clone_to_uninit(&self, dst: *mut T)
unsafe fn clone_to_uninit(&self, dst: *mut T)
clone_to_uninit
)