Struct stm32_metapac::i3c::regs::Timingr2
#[repr(transparent)]pub struct Timingr2(pub u32);
Expand description
I3C timing register 2.
Tuple Fields§
§0: u32
Implementations§
§impl Timingr2
impl Timingr2
pub const fn stallt(&self) -> bool
pub const fn stallt(&self) -> bool
Controller clock stall on T-bit phase of Data enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase (before 9th bit). This allows the target to prepare data to be sent.
pub fn set_stallt(&mut self, val: bool)
pub fn set_stallt(&mut self, val: bool)
Controller clock stall on T-bit phase of Data enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase (before 9th bit). This allows the target to prepare data to be sent.
pub const fn stalld(&self) -> bool
pub const fn stalld(&self) -> bool
controller clock stall on PAR phase of Data enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase (before 9th bit). This allows the target to read received data.
pub fn set_stalld(&mut self, val: bool)
pub fn set_stalld(&mut self, val: bool)
controller clock stall on PAR phase of Data enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase (before 9th bit). This allows the target to read received data.
pub const fn stallc(&self) -> bool
pub const fn stallc(&self) -> bool
controller clock stall on PAR phase of CCC enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase of common command code (before 9th bit). This allows the target to decode the command.
pub fn set_stallc(&mut self, val: bool)
pub fn set_stallc(&mut self, val: bool)
controller clock stall on PAR phase of CCC enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase of common command code (before 9th bit). This allows the target to decode the command.
pub const fn stalla(&self) -> bool
pub const fn stalla(&self) -> bool
controller clock stall enable on ACK phase The SCL is stalled (during tSCLL_STALLas defined by STALL) in the address ACK/NACK phase (before 9th bit). This allows the target to prepare data or the controller to respond to target interrupt.
pub fn set_stalla(&mut self, val: bool)
pub fn set_stalla(&mut self, val: bool)
controller clock stall enable on ACK phase The SCL is stalled (during tSCLL_STALLas defined by STALL) in the address ACK/NACK phase (before 9th bit). This allows the target to prepare data or the controller to respond to target interrupt.